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Test Number : HPE6-A44
Test Name : Scalable WLAN Design and Implementation (SWDI) 8
Vendor Name : HP
: 67 Dumps Questions

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Scalable WLAN Design and Implementation (SWDI) 8 exam

Unified C-programmable ASIP architecture for multi-regular Viterbi, rapid and LDPC decoding | HPE6-A44 Dumps and Real test Questions with VCE Practice Test

F. Naessens, P. Raghavan, L. Van der Perre, A. Dejonghe IMECLeuven, Belgium

summary:

This paper describes an ASIP decoder template proper for multi-commonplace Viterbi, rapid and LDPC decoding. They demonstrate structure fitness for WLAN, WiMAX and 3GPPLTE requisites, despite the fact quite a lot of other standards can even be mapped, considering the structure is able to assisting any interleaver pattern and programmable in C. The ASIP core consists out of a SIMD with distinctive slots each and every with their dedicated functionality. on account of their block based mostly approach and feasible parallelization decoding approach, each turbo and LDPC have been mapped the use of the same thought. help for Viterbi decoding is made feasible through a dedicated decoding pipeline with radix-four to enhance efficiency well above the difficult throughput and latency necessities of the 802.11n typical. specific instantiations are made to display the flexibility of the architecture. For each and every of these instances, enviornment and throughput is given for a commercial 40nmG expertise, displaying to be aggressive versus other bendy solutions, whereas offering some key differentiators in the feel of flexibility, utilization and particular mode instantiation.

I. INTRODUCTION

current and rising mobile conversation networks are posing excessive requirements and adaptability, which paves the manner for application defined Radio (SDR). a lot of advances were made in the internal modem processing [1][2][3][4], yielding to architectures that present a excessive diploma of parallel processing. The outer modem processing, extra exceptionally in the channel decoding, is specially dominated via dedicated ASIC options.

lately some bendy implementation have been derived which assist multi-regular channel decoding [5][6][7]. These options always have a distinct pipelining for every of the decoding modes. With their answer they want to offer multi-average decoding with optimum hardware re-use and entire bendy reminiscence allocation. Their old answer offered aid for flexible faster and LDPC decoding [8]. although they now have additional extended the architecture with extended purposeful assist and more desirable throughputs whereas having a reduce area footprint. moreover there is a C-compiler with helps mapping functionality. Their solution proves to be flexible (each in assisting multi-average LDPC, faster and LDPC as well as utilization) and performant in comparison to State-of-the-artwork solutions [5][6][7].

The rest of the paper is structured as follows: part II introduces the algorithms and the way parallelization is exploited. In section III, the structure is introduced along side the guideline set and pipelining. Implementation effects and benchmarking are certain in sections IV and V respectively. eventually, section VI will conclude the paper.

II. DECODING ALGORITHM OVERVIEW

In contrary in opposition t Viterbi decoding, low-densityparity- investigate (LDPC) and faster codes are performing very close towards the Shannon limit. The main drawback however is their excessive computational complexity, which paves the style for parallel decoding architectures. in the subsequent subsections all decoding modes could be specific and specific center of attention will be given in opposition t parallel decoding probabilities.

A. Viterbi decoding

Convolutional encoding is obligatory present in lots of verbal exchange requisites. In a convolutional encoder, information bits are being fed into prolong line, from which certain branches are xor-ed and fed to the output. If they agree with WLAN as illustration, the throughput is being wired against decoder output fees of 600 Mbps (in IEEE 802.11n ordinary). Viterbi decoding is a close-finest decoding of convolutional encoded data. It has a strongly decreased complexity and memory requirement compared to choicest decoding. It become introduced through Andrew J. Viterbi in his landmark paper [9].

all over decoding, essentially the most probably direction is being decided in accordance with the (delicate) tips bits and possible prolong line state. above all in Viterbi, a window (with so called trace-returned size) is considered before taking a choice on essentially the most probable course and corresponding decoded bit. A excessive-level view on the decoding operation is depicted on figure 1.

determine 1 : Decoding overview

there is an iterative path involving calculation of the state memory, which will also be damaged into parallel execution by means of making use of a radix-2Z also known as look-forward aspect Z [10]. within the final of this paper they are able to center of attention on a Viterbi decoder suitable for WLAN operation, with polynomials equal to 133oct, 171oct. there is mounted decoding pipeline with committed registers for which a high level diagram is depicted on figure 2. they have applied a glance-ahead of aspect 2 (also known as radix-four implementation), which might influence in throughput performance equal to 2 output bits per clock cycle.

determine 2 : Viterbi decoding pipeline

B. rapid decoding

Decoding a turbo code requires iterating optimum a posteriori (MAP) decoding of the constituent codes and (de)interleaving operations. they now have chosen to make use of the log-MAP with max* approximation. The parallelization of the log-MAP can also be performed both by augmenting the radix factor [11] or by computing in parallel dissimilar “windows” out of the coded block [12]. figure 1 depicts the operation of a parallel log-MAP decoder with parallel windows. The excellent half (a) recalls the classical sliding windows log-MAP decoding circulation. A forward recursion, given by means of (1) is applied to the input image metrics (g). part of the backward recursion (2) is started after a window of M inputs is handled by using the forward recursion. The recursion is then initialized both the usage of a practicing sequence applied on the image metrics from the adjoining window, or using backward state metrics (b) from a old new release (subsequent new release initialization, NII). in line with the state metrics output of the forward (a) and backward (b) recursions, next to the input symbol metrics (g), the log-MAP outputs (extrinsic guidance, e) will also be computed. the usage of NII is favored as it ends up in greater regular facts movement. That approach, as shown in the bottom a part of the determine (b), the log-MAP decoding can readily be parallelized by means of computing a couple of home windows in parallel.

determine 3 : Parallel log-MAP decoder

besides the log-MAP, interleaving operations ought to even be parallelized. As interleaving capability intrinsically permutation the records out of a reminiscence, parallelizing it requires to use assorted memory banks and address skills collision in examine and write operations. For this, collision free interleaving patterns or collision-resolution architectures were proposed in [13] and [14] respectively. Later, Tarable proved in [15] that any interleaving law may also be mapped onto any parallel multi-banked architecture. He also proposed an annealing algorithm it is confirmed to all the time converge to a valid mapping function.

during this work, we're capitalizing on the multi-window log-MAP parallelization mixed with Tarable’s interleaving law mapping. Contrarily as what they did in [12] although, they do not parallelize the ahead and backward recursion anymore. here is to permit single guideline assorted facts (SIMD) implementation of the datapath. If SIMD is used to parallelize assorted windows, a restriction is that the identical operation has to be applied to the entire parallelized home windows on the equal time. With their usual parallelization [12], each and every “employee” (structure implementing two adjacent windows) had to operate forward and backward steps in parallel, which is inconceivable in SIMD. additionally, for a similar purpose, the computation of gs, as and bs over the branches or states are serialized.

C. LDPC decoding

When when you consider that a (n,ok) LDPC code, with ok counsel bits and n coded bits the parity assess matrix H is of dimension [(n-k) × n]. Simulations have proven that the layered decoding reduces the variety of iterations crucial to converge [16][17]. In layered decoding [18] the parity determine matrix has to be decomposable into m sub-matrices with dimension [z×n], often known as super-codes as depicted on determine 2. For each super-code, the place of 1s is proscribed such that, per column in a brilliant-code, best zero or one non-zero point is allowed. For the standards in scope this property is either immediately met, during the undeniable fact that the sub-matrices in the super-codes are either zero matrices or cyclic permuted id matrices, or may also be derived.

determine 4 : LDPC Layered Decoding

due to the latter property, inside a layer, the check node updates and corresponding bit node updates will also be accomplished in parallel considering that there is only one edge from every bit node against a verify node in a layer. Intrinsically this allows z parallel processing threads every performing determine node updates and message node updates akin to a row inside the layer of the parity determine matrix. a top level view of the viable z values inside the requisites in scope is summarized in desk 1. with a purpose to obtain the top-rated BER performance, the turbodecoder- based method, with the max* [16] approximation is appreciated. within the z parallel processing threads, the calculation of the ahead and backward recursion metrics as smartly because the bit node replace messages will also be calculated.

table 1 : z-cost within requirements in Scope

III. structure OVERVIEW

in accordance with the parallelization intrinsically present within the algorithms specific in area II, a SIMD implementation covers the constraints. an outline of the structure is depicted on determine 5.

The structure exists out of a SIMD engine related to scalar facts memory and two (native) vector reminiscences. so as to agree to all permutation and interleaving patterns, the history memory is connected via a crossbar. each the handle and the crossbar control are configured via search for desk which is using via a digital tackle.

The SIMD engine changed into developed the usage of goal tool suite [19], offering next to high degree modeling of processor components additionally a C-compiler to efficaciously discover and map the decoding purposes. There are six parallel slots for which the primary one is working on scalar container best and specially used for initialization and loop handle. The processor has following properties:

  • guide width of eighty bits
  • scalar be aware width of 12 bits (signed)
  • vector be aware width of eight bits (signed)
  • sixteen scalar registers
  • eight vector registers
  • highest pipeline depth of eight (handiest utilized for loads from background vector memory)
  • Stack applied on DM and VMEM memory
  • The instruction set is depicted on table 2. The guideline set is rather constrained and still presents help for many of the C-code constructs.

    figure 5 : structure overview

    table 2 : instruction set overview

    An illustration of a firmware kernel and it corresponding meeting can also be found in table three and desk four. The code is a part of the LDPC decoding which decodes a layer present out of 6 non-zero parity examine sub-matrices. The loops are automatically unrolled (through compiler directives) and mapped onto 29 cycles.

    table three : Firmware C-code illustration

    The slot utilization for the distinct processing kernels is depicted on figure 4. you'll be able to clearly observe that the viterbi decoding kernel doesn’t make the most of the vector alu and native vector reminiscence slots. In ordinary, a somewhat dense schedule is carried out, definitely deliberating the very constrained variety of vector registers. increasing the number of vector registers would be a good idea for the time table, however would drastically raise the occupied enviornment and energy consumption of the SIMD processing core.

    determine 6 : Slot utilization [%] for the distinctive processing kernels (rapid, ldpc, viterbi)

    desk 4 : resulting meeting code mapped over diverse ASIP core slots

    IV. IMPLEMENTATION consequences

    A. Template instantiation

    based on the necessities of the decoding modes a parallelization of ninety six slots is selected. They regarded three distinct cases for which the supporting modes are summarized in desk 5. in order to permit a assessment, interior quantization was fastened against eight bit for all instantiations.

    table 5 : distinctive instantiations

    The mapping onto the memory hierarchy for each and every of the decoding modes is depicted on figure 7. given that the Viterbi decoding has a committed pipeline, there isn't any need for utilization of the local vector reminiscence. The memory requirements are obviously driven with the aid of the turbo decoding mode.

    figure 5 : Variable mapping onto reminiscence hierarchy for distinct deocoding modes

    an outline of the implementation particulars for every of the circumstances is given in desk 6. In case of the LDPC handiest illustration, considerable volume of complexity can also be avoided. First the variety of scalar and vector registers can be reduced tremendously without sacrificing throughput performance; secondly the complete crossbar can get replaced through a rotation engine (barrel shifter) as a result of the homes interior the WLAN and WiMAX LDPC codes. On accurate of that the memory necessities are a great deal decrease and the historical past memory doesn’t need to be segmented separately over the ninety six-slots.

    desk 6 : implementation particulars for distinctive situations

    B. enviornment

    For the implementation, a 0.9V 40nm technique was selected. good judgment synthesis become carried out using commercial equipment and a floorplan utilization of 60% was taken into account. reminiscence area is based on macros of commercial attainable reminiscence IP supplier. In figure 6 that you can locate the enviornment for the ASIP core for each of the template instantiations, which obviously shows the high area impact of the vector registers and the overhead of Viterbi decoding as completely unbiased pipeline (contribution each in ‘alu vector spec’ as in ‘different regs’). The usual area for each and every of the situations will also be found in desk 7, which clearly indicates the architecture is memory dominated and for this memory constraints, the 3PP-LTE rapid decoding mode is probably the most demanding one.

    figure 8 : ASIP area distribution for distinctive situations

    table 7 : universal enviornment overview for diverse situations

    C. Throughput

    an outline of one of the crucial throughputs which can be done are shown in table 8. As for the Viterbi decoding, the throughput is drawing near a two output bits per clock cycle. The overhead is coming from the reminiscence entry and loop handle

    table 8 : Throughput results for 800MHz clock frequency

    D. vigour/power effectivity

    an outline of the power consumption and in accordance decoding energy effectivity is depicted on figure 9 and figure 10 respectively. The leakage is comparatively small compared to the dynamic power consumption. The vigor consumption (therefore additionally energy efficiency) is a bit increasing from the LDPC best instance compared to the complete flexible solution.

    determine 9 : ASIP vigour consumption

    determine 10 : Decoding efficiency for distinctive modes mapped onto distinctive instances

    V. comparison VERSUS STATE-OF-THE-art

    evaluation of their answer versus other bendy options is shown on determine 11. All solutions have been compared with a throughput over good judgment-area metric, were enviornment numbers had been scaled against 40nm expertise. Their solution demonstrate to be very aggressive versus different solutions and extra tuning is viable when putting off the Viterbi and/or rapid decoding mode guide. On precise of that they present a excessive degree of flexibility via guide of any interleaver pattern and C-programmable core. additionally, one of the vital proposed options [5][6] should not able to meet the annoying latency and throughput constraints posed by means of the WLAN ordinary.

    determine 11 : flexible multi-general assessment (based on throughput/common sense-area ratio)

    VI. CONCLUSIONS

    we now have proven a flexible structure which may also be considered as a template acceptable for multi-usual multi-mode LDPC, faster and Viterbi decoding. both LDPC and faster can be properly parallelized to be mapped onto a SIMD engine. with a purpose to raise the throughput, the SIMD engine consists out of parallel slots, each with their committed performance. Viterbi assist is enabled through a committed pipeline for which they have selected a radix-four for greater throughput.

    Some particular instantiations of the template were applied in a industrial 40nmG expertise and display to be aggressive versus different state-of-the-paintings solutions, while offering clear merits in flexibility, utilization and particular mode instantiation.

    REFERENCES

    [1] B. Bougard et al., “energy effective utility defined Radio options for MIMO-based mostly Broadband communication”, Proc. European signal Processing convention, Sept. 2007”

    [2] B. Bougard et al., “a rough-Grained Array based Baseband Processor for 100Mbps+ software described Radio”, Design Automation and examine in Europe, March 2008

    [3] J. Glossner et al., “The Sandblaster SB3011 platform”, EURASIP Journal on Embedded methods, 2007

    [4] Yuan Lee et al., “SODA: A high-performance DSP structure for utility-defined Radio”, IEEE Micro, 2007

    [5] Alles M, Vogt T, Wehn N. FlexiChaP: A reconfigurable ASIP for convolutional, turbo, and LDPC code decoding. 2008 fifth foreign Symposium on rapid Codes and linked topics.

    [6] Kunze S, Matuˇ E, Corp NEC. A ” Multi-person ” strategy against a channel decoder for convolutional, turbo and LDPC codes, TU Dresden Vodafone Chair mobile Comm . techniques system IP core analysis labs. structure. 2010:390-395.

    [7] solar Y, Cavallaro JR. a versatile LDPC/rapid Decoder structure. Journal of sign Processing programs. 2010;(November 2009).

    [8] Naessens F, Derudder V, Cappelle H, et al. and decoder for 802 . 11n , 802 . 16e and 3GPP-LTE. VLSI symposium. 2010:213-214

    [9] Andrew J. Viterbi, ”Error bounds for convolutional codes and an asymptotically optimum decoding algorithm”, IEEE Transactions on counsel concept 13(2):260–269, April 1967

    [10] G. Fettweis and H. Meyr, “high-velocity Parallel Viterbi Decoding: Algorithm and VLSI-architecture“, IEEE Comm. magazine, may 1991.

    [11] M Bickerstaff et al., “A 24Mb/s radix-four logMAP faster decoder for 3GPP-HSDPA cell instant”, ISSCC, Feb 2003

    [12] B. Bougard et al., “A scalable 8.7 nJ/bit seventy five.6 Mb/s parallel concatenated convolutional (faster-) CODEC”, ISSCC, Feb. 2003

    [13] Giulietti, A.; van der Perre, L.; Strum, A., "Parallel faster coding interleavers: heading off collisions in accesses to storage features," Electronics Letters , vol.38, no.5, pp.232-234, 28 Feb 2002

    [14] Thul, M.J et al, "A scalable gadget structure for highthroughput turbo-decoders," IEEE Workshop on sign Processing programs, 2002, pp. 152-158

    [15] Tarable, A.; Benedetto, S.; Montorsi, G., "Mapping interleaving laws to parallel rapid and LDPC decoder architectures", IEEE Transactions on advice idea, vol.50, no.9, pp. 2002-2009, Sept. 2004

    [16] M. Mansour and N. Shabhag, “excessive-throughput LDPC decoders”, IEEE Trans. VLSI Syst., eleven(6): pages 976-996, Dec 2003 [17] R. Priewasser, M. Huemer, B. Bougard, “trade-off analysis of decoding algorithms and architectures for multi-general LDPC decoder”, IEEE Workshop on sign Processing methods, 2008.

    [18] D. Hocevar, “A decreased Complexity Decoder architecture via Layered Decoding of LDPC Codes”, IEEE Workshop on signal Processing methods, 2004, pages 107-112.

    [19] goal Compiler applied sciences, http://www.retarget.com/ 


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    References :


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